PERF_TYPE_HARDWARE

This indicates one of the "generalized" hardware events provided by the kernel. See the config field definition for more details.

PERF_TYPE_SOFTWARE

This indicates one of the software-defined events provided by the kernel (even if no hardware support is available).

PERF_TYPE_TRACEPOINT

This indicates a tracepoint provided by the kernel tracepoint infrastructure.

PERF_TYPE_HW_CACHE

This indicates a hardware cache event. This has a special encoding, described in the config field definition.

PERF_TYPE_RAW

This indicates a "raw" implementation-specific event in the config field.

PERF_TYPE_BREAKPOINT (Since Linux 2.6.33)

This indicates a hardware breakpoint as provided by the CPU. Breakpoints can be read/write accesses to an address as well as execution of an instruction address.

dynamic PMU

Since Linux 2.6.39, perf_event_open() can support multiple PMUs. To enable this, a value exported by the kernel can be used in the type field to indicate which PMU to use. The value to use can be found in the sysfs filesystem: there is a subdirectory per PMU instance under /sys/bus/event_source/devices. In each sub-directory there is a type file whose content is an integer that can be used in the type field. For instance, /sys/bus/event_source/devices/cpu/type contains the value for the core CPU PMU, which is usually 4.

PERF_COUNT_HW_CPU_CYCLES

Total cycles. Be wary of what happens during CPU frequency scaling.

PERF_COUNT_HW_INSTRUCTIONS

Retired instructions. Be careful, these can be affected by various issues, most notably hardware interrupt counts.

PERF_COUNT_HW_CACHE_REFERENCES

Cache accesses. Usually this indicates Last Level Cache accesses but this may vary depending on your CPU. This may include prefetches and coherency messages; again this depends on the design of your CPU.

PERF_COUNT_HW_CACHE_MISSES

Cache misses. Usually this indicates Last Level Cache misses; this is intended to be used in conjunction with the PERF_COUNT_HW_CACHE_REFERENCES event to calculate cache miss rates.

PERF_COUNT_HW_BRANCH_INSTRUCTIONS

Retired branch instructions. Prior to Linux 2.6.34, this used the wrong event on AMD processors.

PERF_COUNT_HW_BRANCH_MISSES

Mispredicted branch instructions.

PERF_COUNT_HW_BUS_CYCLES

Bus cycles, which can be different from total cycles.

PERF_COUNT_HW_STALLED_CYCLES_FRONTEND (Since Linux 3.0)

Stalled cycles during issue.

PERF_COUNT_HW_STALLED_CYCLES_BACKEND (Since Linux 3.0)

Stalled cycles during retirement.

PERF_COUNT_HW_REF_CPU_CYCLES (Since Linux 3.3)

Total cycles; not affected by CPU frequency scaling.

PERF_COUNT_SW_CPU_CLOCK

This reports the CPU clock, a high-resolution per-CPU timer.

PERF_COUNT_SW_TASK_CLOCK

This reports a clock count specific to the task that is running.

PERF_COUNT_SW_PAGE_FAULTS

This reports the number of page faults.

PERF_COUNT_SW_CONTEXT_SWITCHES

This counts context switches. Until Linux 2.6.34, these were all reported as user-space events, after that they are reported as happening in the kernel.

PERF_COUNT_SW_CPU_MIGRATIONS

This reports the number of times the process has migrated to a new CPU.

PERF_COUNT_SW_PAGE_FAULTS_MIN

This counts the number of minor page faults. These did not require disk I/O to handle.

PERF_COUNT_SW_PAGE_FAULTS_MAJ

This counts the number of major page faults. These required disk I/O to handle.

PERF_COUNT_SW_ALIGNMENT_FAULTS (Since Linux 2.6.33)

This counts the number of alignment faults. These happen when unaligned memory accesses happen; the kernel can handle these but it reduces performance. This happens only on some architectures (never on x86).

PERF_COUNT_SW_EMULATION_FAULTS (Since Linux 2.6.33)

This counts the number of emulation faults. The kernel sometimes traps on unimplemented instructions and emulates them for user space. This can negatively impact performance.

If type is PERF_TYPE_TRACEPOINT, then we are measuring kernel tracepoints. The value to use in config can be obtained from under debugfs tracing/events/*/*/id if ftrace is enabled in the kernel.

If type is PERF_TYPE_HW_CACHE, then we are measuring a hardware CPU cache event. To calculate the appropriate config value use the following equation:

    (perf_hw_cache_id) | (perf_hw_cache_op_id << 8) |
    (perf_hw_cache_op_result_id << 16)

where perf_hw_cache_id is one of:

PERF_COUNT_HW_CACHE_L1D

for measuring Level 1 Data Cache

PERF_COUNT_HW_CACHE_L1I

for measuring Level 1 Instruction Cache

PERF_COUNT_HW_CACHE_LL

for measuring Last-Level Cache

PERF_COUNT_HW_CACHE_DTLB

for measuring the Data TLB

PERF_COUNT_HW_CACHE_ITLB

for measuring the Instruction TLB

PERF_COUNT_HW_CACHE_BPU

for measuring the branch prediction unit

PERF_COUNT_HW_CACHE_NODE (Since Linux 3.0)

for measuring local memory accesses

and perf_hw_cache_op_id is one of

PERF_COUNT_HW_CACHE_OP_READ

for read accesses

PERF_COUNT_HW_CACHE_OP_WRITE

for write accesses

PERF_COUNT_HW_CACHE_OP_PREFETCH

for prefetch accesses

and perf_hw_cache_op_result_id is one of

PERF_COUNT_HW_CACHE_RESULT_ACCESS

to measure accesses

PERF_COUNT_HW_CACHE_RESULT_MISS

to measure misses

If type is PERF_TYPE_RAW, then a custom "raw" config value is needed. Most CPUs support events that are not covered by the "generalized" events. These are implementation defined; see your CPU manual (for example the Intel Volume 3B documentation or the AMD BIOS and Kernel Developer Guide). The libpfm4 library can be used to translate from the name in the architectural manuals to the raw hex value perf_event_open() expects in this field.

If type is PERF_TYPE_BREAKPOINT, then leave config set to zero. Its parameters are set in other places.

PERF_SAMPLE_IP

Records instruction pointer.

PERF_SAMPLE_TID

Records the process and thread IDs.

PERF_SAMPLE_TIME

Records a timestamp.

PERF_SAMPLE_ADDR

Records an address, if applicable.

PERF_SAMPLE_READ

Record counter values for all events in a group, not just the group leader.

PERF_SAMPLE_CALLCHAIN

Records the callchain (stack backtrace).

PERF_SAMPLE_ID

Records a unique ID for the opened event's group leader.

PERF_SAMPLE_CPU

Records CPU number.

PERF_SAMPLE_PERIOD

Records the current sampling period.

PERF_SAMPLE_STREAM_ID

Records a unique ID for the opened event. Unlike PERF_SAMPLE_ID the actual ID is returned, not the group leader. This ID is the same as the one returned by PERF_FORMAT_ID.

PERF_SAMPLE_RAW

Records additional data, if applicable. Usually returned by tracepoint events.

PERF_SAMPLE_BRANCH_STACK (Since Linux 3.4)

This provides a record of recent branches, as provided by CPU branch sampling hardware (such as Intel Last Branch Record). Not all hardware supports this feature.

See the branch_sample_type field for how to filter which branches are reported.

PERF_SAMPLE_REGS_USER (Since Linux 3.7)

Records the current user-level CPU register state (the values in the process before the kernel was called).

PERF_SAMPLE_STACK_USER (Since Linux 3.7)

Records the user level stack, allowing stack unwinding.

PERF_SAMPLE_WEIGHT (Since Linux 3.10)

Records a hardware provided weight value that expresses how costly the sampled event was. This allows the hardware to highlight expensive events in a profile.

PERF_SAMPLE_DATA_SRC (Since Linux 3.10)

Records the data source: where in the memory hierarchy the data associated with the sampled instruction came from. This is only available if the underlying hardware supports this feature.

PERF_FORMAT_TOTAL_TIME_ENABLED

Adds the 64-bit time_enabled field. This can be used to calculate estimated totals if the PMU is overcommitted and multiplexing is happening.

PERF_FORMAT_TOTAL_TIME_RUNNING

Adds the 64-bit time_running field. This can be used to calculate estimated totals if the PMU is overcommitted and multiplexing is happening.

PERF_FORMAT_ID

Adds a 64-bit unique value that corresponds to the event group.

PERF_FORMAT_GROUP

Allows all counter values in an event group to be read with one read.

0 -

SAMPLE_IP can have arbitrary skid.

1 -

SAMPLE_IP must have constant skid.

2 -

SAMPLE_IP requested to have 0 skid.

3 -

SAMPLE_IP must have 0 skid. See also PERF_RECORD_MISC_EXACT_IP.

HW_BREAKPOINT_EMPTY

No breakpoint.

HW_BREAKPOINT_R

Count when we read the memory location.

HW_BREAKPOINT_W

Count when we write the memory location.

HW_BREAKPOINT_RW

Count when we read or write the memory location.

HW_BREAKPOINT_X

Count when we execute code at the memory location.

The values can be combined via a bitwise or, but the combination of HW_BREAKPOINT_R or HW_BREAKPOINT_W with HW_BREAKPOINT_X is not allowed.

PERF_SAMPLE_BRANCH_USER

Branch target is in user space.

PERF_SAMPLE_BRANCH_KERNEL

Branch target is in kernel space.

PERF_SAMPLE_BRANCH_HV

Branch target is in hypervisor.

PERF_SAMPLE_BRANCH_PLM_ALL

A convenience value that is the three preceding values ORed together.

In addition to the privilege value, at least one or more of the following bits must be set.

PERF_SAMPLE_BRANCH_ANY

Any branch type.

PERF_SAMPLE_BRANCH_ANY_CALL

Any call branch.

PERF_SAMPLE_BRANCH_ANY_RETURN

Any return branch.

PERF_SAMPLE_BRANCH_IND_CALL

Indirect calls.

PERF_SAMPLE_BRANCH_ABORT_TX (Since Linux 3.11)

Transactional memory aborts.

PERF_SAMPLE_BRANCH_IN_TX (Since Linux 3.11)

Branch in transactional memory transaction.

PERF_SAMPLE_BRANCH_NO_TX (Since Linux 3.11)

Branch not in transactional memory transaction.

u32 seq, time_mult, time_shift, idx, width;
u64 count, enabled, running;
u64 cyc, time_offset;
s64 pmc = 0;

do {
    seq = pc−>lock;
    barrier();
    enabled = pc−>time_enabled;
    running = pc−>time_running;

    if (pc−>cap_usr_time && enabled != running) {
        cyc = rdtsc();
        time_offset = pc−>time_offset;
        time_mult   = pc−>time_mult;
        time_shift  = pc−>time_shift;
    }

    idx = pc−>index;
    count = pc−>offset;

    if (pc−>cap_usr_rdpmc && idx) {
        width = pc−>pmc_width;
        pmc = rdpmc(idx − 1);
    }

    barrier();
} while (pc−>lock != seq);

pmc <<= 64 − pmc_width;
pmc >>= 64 − pmc_width; // signed shift right
count += pmc;

PERF_RECORD_MISC_CPUMODE_UNKNOWN

Unknown CPU mode.

PERF_RECORD_MISC_KERNEL

Sample happened in the kernel.

PERF_RECORD_MISC_USER

Sample happened in user code.

PERF_RECORD_MISC_HYPERVISOR

Sample happened in the hypervisor.

PERF_RECORD_MISC_GUEST_KERNEL

Sample happened in the guest kernel.

PERF_RECORD_MISC_GUEST_USER

Sample happened in guest user code.

In addition, one of the following bits can be set:

PERF_RECORD_MISC_MMAP_DATA

This is set when the mapping is not executable; otherwise the mapping is executable.

PERF_RECORD_MISC_EXACT_IP

This indicates that the content of PERF_SAMPLE_IP points to the actual instruction that triggered the event. See also perf_event_attr.precise_ip.

PERF_RECORD_MISC_EXT_RESERVED

This indicates there is extended data available (currently not used).

PERF_RECORD_MMAP

The MMAP events record the PROT_EXEC mappings so that we can correlate user-space IPs to code. They have the following structure:

struct	{
	struct perf_event_header		header;
	u32		pid,
			tid;
	u64		addr;
	u64		len;
	u64		pgoff;
	char		filename[];
};

PERF_RECORD_LOST

This record indicates when events are lost.

struct	{
	struct perf_event_header		header;
	u64		id;
	u64		lost;
};

id

is the unique event ID for the samples that were lost.

lost

is the number of events that were lost.

PERF_RECORD_COMM

This record indicates a change in the process name.

struct	{
	struct perf_event_header		header;
	u32		pid,
			tid;
	char		comm[];
};

PERF_RECORD_EXIT

This record indicates a process exit event.

struct	{
	struct perf_event_header		header;
	u32		pid,
			ppid;
	u32		tid,
			ptid;
	u64		time;
};

PERF_RECORD_THROTTLE, PERF_RECORD_UNTHROTTLE

This record indicates a throttle/unthrottle event.

struct	{
	struct perf_event_header		header;
	u64		time;
	u64		id;
	u64		stream_id;
};

PERF_RECORD_FORK

This record indicates a fork event.

struct	{
	struct perf_event_header		header;
	u32		pid,
			ppid;
	u32		tid,
			ptid;
	u64		time;
};

PERF_RECORD_READ

This record indicates a read event.

struct	{
	struct perf_event_header		header;
	u32		pid,
			tid;
	struct read_format		values;
};

PERF_RECORD_SAMPLE

This record indicates a sample.

struct {
    struct perf_event_header header;
    u64   ip;         /* if PERF_SAMPLE_IP */
    u32   pid, tid;   /* if PERF_SAMPLE_TID */
    u64   time;       /* if PERF_SAMPLE_TIME */
    u64   addr;       /* if PERF_SAMPLE_ADDR */
    u64   id;         /* if PERF_SAMPLE_ID */
    u64   stream_id;  /* if PERF_SAMPLE_STREAM_ID */
    u32   cpu, res;   /* if PERF_SAMPLE_CPU */
    u64   period;     /* if PERF_SAMPLE_PERIOD */
    struct read_format v; /* if PERF_SAMPLE_READ */
    u64   nr;         /* if PERF_SAMPLE_CALLCHAIN */
    u64   ips[nr];    /* if PERF_SAMPLE_CALLCHAIN */
    u32   size;       /* if PERF_SAMPLE_RAW */
    char  data[size]; /* if PERF_SAMPLE_RAW */
    u64   bnr;        /* if PERF_SAMPLE_BRANCH_STACK */
    struct perf_branch_entry lbr[bnr];
                      /* if PERF_SAMPLE_BRANCH_STACK */
    u64   abi;        /* if PERF_SAMPLE_REGS_USER */
    u64   regs[weight(mask)];
                      /* if PERF_SAMPLE_REGS_USER */
    u64   size;       /* if PERF_SAMPLE_STACK_USER */
    char  data[size]; /* if PERF_SAMPLE_STACK_USER */
    u64   dyn_size;   /* if PERF_SAMPLE_STACK_USER */
    u64   weight;     /* if PERF_SAMPLE_WEIGHT */
    u64   data_src;   /* if PERF_SAMPLE_DATA_SRC */
};

ip

If PERF_SAMPLE_IP is enabled, then a 64-bit instruction pointer value is included.

pid, tid

If PERF_SAMPLE_TID is enabled, then a 32-bit process ID and 32-bit thread ID are included.

time

If PERF_SAMPLE_TIME is enabled, then a 64-bit timestamp is included. This is obtained via local_clock() which is a hardware timestamp if available and the jiffies value if not.

addr

If PERF_SAMPLE_ADDR is enabled, then a 64-bit address is included. This is usually the address of a tracepoint, breakpoint, or software event; otherwise the value is 0.

id

If PERF_SAMPLE_ID is enabled, a 64-bit unique ID is included. If the event is a member of an event group, the group leader ID is returned. This ID is the same as the one returned by PERF_FORMAT_ID.

stream_id

If PERF_SAMPLE_STREAM_ID is enabled, a 64-bit unique ID is included. Unlike PERF_SAMPLE_ID the actual ID is returned, not the group leader. This ID is the same as the one returned by PERF_FORMAT_ID.

cpu, res

If PERF_SAMPLE_CPU is enabled, this is a 32-bit value indicating which CPU was being used, in addition to a reserved (unused) 32-bit value.

period

If PERF_SAMPLE_PERIOD is enabled, a 64-bit value indicating the current sampling period is written.

v

If PERF_SAMPLE_READ is enabled, a structure of type read_format is included which has values for all events in the event group. The values included depend on the read_format value used at perf_event_open() time.

nr, ips[nr]

If PERF_SAMPLE_CALLCHAIN is enabled, then a 64-bit number is included which indicates how many following 64-bit instruction pointers will follow. This is the current callchain.

size, data[size]

If PERF_SAMPLE_RAW is enabled, then a 32-bit value indicating size is included followed by an array of 8-bit values of length size. The values are padded with 0 to have 64-bit alignment.

This RAW record data is opaque with respect to the ABI. The ABI doesn't make any promises with respect to the stability of its content, it may vary depending on event, hardware, and kernel version.

bnr, lbr[bnr]

If PERF_SAMPLE_BRANCH_STACK is enabled, then a 64-bit value indicating the number of records is included, followed by bnr perf_branch_entry structures which each include the fields:

from

This indicates the source instruction (may not be a branch).

to

The branch target.

mispred

The branch target was mispredicted.

predicted

The branch target was predicted.

in_tx (Since Linux 3.11)

The branch was in a transactional memory transaction.

abort (Since Linux 3.11)

The branch was in an aborted transactional memory transaction.

The entries are from most to least recent, so the first entry has the most recent branch.

Support for mispred and predicted is optional; if not supported, both values will be 0.

The type of branches recorded is specified by the branch_sample_type field.

abi, regs[weight(mask)]

If PERF_SAMPLE_REGS_USER is enabled, then the user CPU registers are recorded.

The abi field is one of PERF_SAMPLE_REGS_ABI_NONE, PERF_SAMPLE_REGS_ABI_32 or PERF_SAMPLE_REGS_ABI_64.

The regs field is an array of the CPU registers that were specified by the sample_regs_user attr field. The number of values is the number of bits set in the sample_regs_user bitmask.

size, data[size], dyn_size

If PERF_SAMPLE_STACK_USER is enabled, then record the user stack to enable backtracing. size is the size requested by the user in stack_user_size or else the maximum record size. data is the stack data. dyn_size is the amount of data actually dumped (can be less than size).

weight

If PERF_SAMPLE_WEIGHT is enabled, then a 64 bit value provided by the hardware is recorded that indicates how costly the event was. This allows expensive events to stand out more clearly in profiles.

data_src

If PERF_SAMPLE_DATA_SRC is enabled, then a 64 bit value is recorded that is made up of the following fields:

mem_op

Type of opcode, a bitwise combination of:

PERF_MEM_OP_NA

Not available

PERF_MEM_OP_LOAD

Load instruction

PERF_MEM_OP_STORE

Store instruction

PERF_MEM_OP_PFETCH

Prefetch

PERF_MEM_OP_EXEC

Executable code

mem_lvl

Memory hierarchy level hit or miss, a bitwise combination of:

PERF_MEM_LVL_NA

Not available

PERF_MEM_LVL_HIT

Hit

PERF_MEM_LVL_MISS

Miss

PERF_MEM_LVL_L1

Level 1 cache

PERF_MEM_LVL_LFB

Line fill buffer

PERF_MEM_LVL_L2

Level 2 cache

PERF_MEM_LVL_L3

Level 3 cache

PERF_MEM_LVL_LOC_RAM

Local DRAM

PERF_MEM_LVL_REM_RAM1

Remote DRAM 1 hop

PERF_MEM_LVL_REM_RAM2

Remote DRAM 2 hops

PERF_MEM_LVL_REM_CCE1

Remote cache 1 hop

PERF_MEM_LVL_REM_CCE2

Remote cache 2 hops

PERF_MEM_LVL_IO

I/O memory

PERF_MEM_LVL_UNC

Uncached memory

mem_snoop

Snoop mode, a bitwise combination of:

PERF_MEM_SNOOP_NA

Not available

PERF_MEM_SNOOP_NONE

No snoop

PERF_MEM_SNOOP_HIT

Snoop hit

PERF_MEM_SNOOP_MISS

Snoop miss

PERF_MEM_SNOOP_HITM

Snoop hit modified

mem_lock

Lock instruction, a bitwise combination of:

PERF_MEM_LOCK_NA

Not available

PERF_MEM_LOCK_LOCKED

Locked transaction

mem_dtlb

TLB access hit or miss, a bitwise combination of:

PERF_MEM_TLB_NA

Not available

PERF_MEM_TLB_HIT

Hit

PERF_MEM_TLB_MISS

Miss

PERF_MEM_TLB_L1

Level 1 TLB

PERF_MEM_TLB_L2

Level 2 TLB

PERF_MEM_TLB_WK

Hardware walker

PERF_MEM_TLB_OS

OS fault handler